1. Field of the Invention
The present invention relates to a chip package structure and process of fabricating the same. More particularly, the present invention relates to an ultra-thin chip package structure for mobile communication and process of fabricating the same.
2. Description of the Related Art
In this fast and ever-changing society, information matters to all people. Many types of portable electronic devices are produced with an attempt to catch up with our desires to transmit and receive more data. Due to this trend, manufacturers have tried hard to factor into their chip package as many design concepts as possible including digital layout, network organization, local area connection and personalized of electronic devices. To do so demands special consideration in every aspect of the design process that affects the processing speed, multifunctional capability, integration level, weight and cost of the chip package. In other words, chip packages must be miniaturized and densified. Flip chip (F/C) bonding technique, through the bonding of bumps to a carrier, is currently one of the principle means of reducing overall wiring length over the conventional wire-bonding method. With a shortening of wiring length in a F/C package, signal transmission rate between the chip and a carrier is increased. Thus, F/C packaging technique is one of the most popular techniques for forming high-density packages.
FIG. 1 is a schematic cross-sectional view of a chip package structure fabricated through a conventional flip-chip packaging technique. As shown in FIG. 1, the chip package structure 10 mainly comprises a chip 50, a carrier 80 and an encapsulating material layer 70. The chip 50 has an active surface 52 with a plurality of bonding pads (not shown) thereon. The carrier 80 also has a plurality of contact pads (not shown) thereon. A plurality of bumps 60 is positioned on the respective bonding pads on the active surface 52 of the chip 50. Furthermore, the bonding pads on the chip 50 and the contact pads on the carrier 80 are electrically connected together through the bumps 60. On the far side of the carrier 80 away from the chip 50, an array of solder balls 90 is attached. In other words, the chip package structure 10 has a ball grid array (BGA) packaging structure for connecting electrically with a printed circuit board (PCB).
To prevent any damage to the chip 50 due to an incursion of moisture and any damage to the bumps 60 due to mechanical stress, an encapsulating material layer 70 is formed in the bonding gap between the chip 50 and the carrier 80. Conventionally, the encapsulating material layer 70 is formed by channeling a liquid encapsulating material with low viscosity into the bonding gap between the chip 50 and the carrier 80 through capillary effect and then curing the injected material afterwards.
As mentioned before, the flip-chip package structure 10 as shown in FIG. 1 has an electrical performance better than the conventional wire-bonded chip package. Furthermore, the flip-chip package structure 10 has an ultra-thin thickness suitable for inserting inside a mobile communication device. However, it takes considerable time to fill up all the interior space between the chip 50 and the carrier 80 with liquid encapsulating material through capillary effect alone. Hence, this method is not particularly suitable for economic mass production. Moreover, the number of bumps 60, the distribution of the bumps 60 inside the package as well as the distance of separation between the flip chip 50 and the carrier 80 are principal factors affecting the flow of liquid encapsulating material. Because the capillary effect is utilized to draw liquid encapsulating material into the space between the chip 50 and the carrier 80, any variation of the liquid flow conditions is likely to hinder the filling process leading to a possibility of formation of voids therein. In other words, reliability of the package will be affected.
In addition, the chip 50 is directly exposed. Hence, the chip 50 is easily damaged when special markings are engraved on the surface of the chip 50 or the chip package structure 10 is picked up using a suction grip at the end of a robotic arm. To avoid these defects, an alternative chip package structure is provided. FIGS. 2A and 2B are cross-sectional views of alternative chip package structures fabricated through another conventional flip-chip packaging technique. As shown in FIG. 2A, an additional over mold layer 72 is formed over the chip package structure 10 in FIG. 1 to protect the chip 50 against possible damage.
However, the need to form an additional over mold layer 72 increases overall processing time resulting a drop in productivity. Moreover, delamination is a likely occurrence at the junction interface between the encapsulating material layer 70 and the over mold layer 72. In other words, overall reliability of the chip package structure 12 will drop.
To avoid delamination and increase productivity, an improved chip package structure 14 is shown in FIG. 2B. As shown in FIG. 2B, a simultaneous molding operation is carried out to form an encapsulating material layer 74 that covers the chip 50 as well as the carrier 80 and fills the bonding gap between the chip 50 and the carrier 80. Although the simultaneous molding process is able to prevent delamination, the encapsulating material layer 74 covering the chip must have a minimum thickness of about 0.2 cm to prevent an incomplete filling. With this design limitation, producing an ultra-thin package suitable for incorporating inside a mobile communication device is almost impossible.